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2.4GHz to 2.5GHz 802.11g/b
RF Transceivers with Integrated PA
Table 15. Register 0 (A3:A0 = 0000)
DATA BITS
D13:D11
D10
D9:D0
RECOMMENDED
000
1
1101000000
DESCRIPTION
Set to recommended value.
Fractional-N PLL Mode Enable. Set 1 to enable the fractional-N PLL or set 0 to enable the
integer-N PLL.
Set to recommended value.
Table 16. Register 1 (A3:A0 = 0001)
DATA BITS
D13
D12
D11:D0
RECOMMENDED
0
1
000110011010
DESCRIPTION
Set to recommended value.
Lock-Detector Output Select. Set to 1 for CMOS Output. Set to 0 for open-drain output. Bit D9
in register (A3:A0 = 0101) enables or disables an internal 30k ? pullup resistor in open-drain
output mode.
Set to recommended value.
Table 17. Register 2 (A3:A0 = 0010)
DATA BITS
D13:D0
RECOMMENDED
01000000000011
Set to recommended value.
DESCRIPTION
This register contains the 8-bit integer portion and 6 LSBs of the fractional portion of the divider ratio of the synthesizer.
Table 18. Register 3 (A3:A0 = 0011)
BIT
D13:D8
D7:D0
RECOMMENDED
00000
01111001
DESCRIPTION
6 LSBs of 20-Bit Fractional Portion of Main Divider
8-Bit Integer Portion of Main Divider. Programmable from 64 to 255.
Table 19. Register 4 (A3:A0 = 0100)
BIT
D13:D0
RECOMMENDED
11011001100110
DESCRIPTION
14 MSBs of 20-Bit Fractional Portion of Main Divider
Table 20. Register 5 (A3:A0 = 0101)
BIT
D13:D10
D9
D8:D6
D5
D4:D3
D2
D1:D0
RECOMMENDED
0000
0
010
1
00
1
00
DESCRIPTION
Set to recommended value.
Lock-Detect Output Internal Pullup Resistor Enable. Set to 1 to enable internal 30k ? pullup
resistor or set to 0 to disable the resistor. Only available when lock-detect, open-drain output
is selected (A3:A0 = 0010, D12 = 1).
Set to recommended value.
Lock-Detect Output Enable. Set to 1 to enable the lock-detect output or set to 0 to disable the
output. The output is high impedance when disabled.
Set to recommended value.
Reference Frequency Divider Ratio to PLL. Set to 0 to divide by 1. Set to 1 to divide by 2.
Set to recommended value.
28
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